The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
The ever-shrinking geometry size brings challenges to semiconductor fabrication. For example, semiconductor device fabrication may involve forming a resist-protection-oxide (RPO) layer over and around protruding structures (e.g., fin structures of FinFETs). However, as device sizes become small enough, the RPO layer formed between adjacent protruding structures may merge with each other. The merged RPO layer is difficult to remove, and its removal may cause other problems that may degrade the electrical performance of the semiconductor device.
Therefore, while existing semiconductor devices and the fabrication thereof have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.